1. Field of the Invention
This invention relates to a memory controller for a multilevel cell memory, and in particular to a memory controller having an ECC circuit which generates error detection/correction codes and performs an error detection and correction for multilevel cells.
2. Description of the Related Art
Flash memory is coming into widespread use primarily in portable data terminals, portable telephone sets, and other portable information equipment. Flash memory is nonvolatile semiconductor memory, which can retain stored data even if the power supply is turned off, and so is widely adopted mainly in battery-driven portable information equipment.
Trends toward greater functionality and broadband communications in recent years have been accompanied by mounting demand for flash memory with greater storage capacity. In order to satisfy such demands, multilevel-cell flash memory has been proposed. Broadly defined, this multilevel-cell memory is memory in which cells store states with three or more values; normally, in this memory cells store 2n states (where n is an integer greater than or equal to 2). Hence if there are four charge states, two bits of data are stored in a single cell; if there are eight charge states, three bits of data are stored in a single cell; and if there are 2n charge states, then n bits of data are stored in a single cell.
Semiconductor memory such as flash memory has a high per-bit cost, and therefore the use of ECC code, which requires numerous bits, is not suited to flash memory. On the other hand, flash memory is more reliable than hard disks or other storage media, with a defect occurring in at most one cell. Hence many conventional one-bit-cell memory devices adopt as the ECC code a Hamming code, for which correction of up to one-bit errors is possible. This is because, for an ECC code capable of correction of errors in a plurality of bits, the number of bits required to the ECC becomes too great, and there is no need for correction of errors in a plurality of bits. That is, when, as in the case of flash memory, the per-bit cost is high, but reliability is high enough that a defect occurs in at most one bit, a Hamming code enabling correction of up to one bit error using a small number of bits is appropriate as the ECC code.
If a defect occurs in a certain cell of a multilevel cell memory supporting large storage capacity, the n bits of data associated with the defective cell may simultaneously become defective bits. Consequently an error correction code using the above Hamming code capable of correction of up to one-bit errors cannot correct the errors in n bits (where n is two or greater) accompanying a single defective cell, and so a different type of ECC code other than the Hamming code, with a greater number of bits, must be used. For example, a complex ECC code adopted in hard disks might be used. However, such ECC codes with a large number of bits are not suited to flash memory with its high per-bit cost.
In order to address the above problem, it has been proposed, in U.S. Pat. No. 5,754,566, that an ECC circuit be provided in a memory device, that this ECC circuit be designed to separate serial data into a plurality of data words, so that within a data word there is only one bit associated with the n bits of one cell, and that an ECC code be generated for each data word, and stored in an n-bit cell.
However, incorporation of an ECC circuit in a memory device will tend to increase the cost of the memory device, and so is undesirable. Particularly in a system in which are installed a plurality of memory devices, the same ECC circuit is provided redundantly in a plurality of memory devices, driving up the cost of the overall system.